On Tue, Nov 07, 2023 at 07:50:52PM +0100, Geert Uytterhoeven wrote:
Hi Sasha,
On Tue, Nov 7, 2023 at 1:21 PM Sasha Levin <sashal@xxxxxxxxxx> wrote:
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
[ Upstream commit c588e1c9846b32182fd5a0ceb637b983810e7100 ]
Enable PCIe Host controller channel 0 on R-Car S4-8 Spider board.
Since this board has an Oculink connector, CLKREQ# pin of PFC for PCIe
should not be used. So, using a GPIO is used to output the clock instead.
Otherwise the controller cannot detect a PCIe device.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Link: https://lore.kernel.org/r/20230905012404.2915246-3-yoshihiro.shimoda.uh@xxxxxxxxxxx
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
Thanks for your patch!
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -145,6 +157,18 @@ &mmc0 {
status = "okay";
};
+&pcie0_clkref {
+ compatible = "gpio-gate-clock";
+ clocks = <&rc21012_pci>;
+ enable-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ /delete-property/ clock-frequency;
+};
+
+&pciec0 {
+ reset-gpio = <&gpio_exp_20 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
These references have a hard dependency on commit 183a709d3719e5c9
("arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes")
in v6.6+ (i.e. v6.7-rc1 soon).
To actually work, this has a soft (runtime) dependency on commit
0d0c551011df4519 ("PCI: rcar-gen4: Add R-Car Gen4 PCIe controller
support for host mode") in v6.6+.
Sounds like I should just drop this patch :)
--
Thanks,
Sasha
