On Tue, 03 Oct 2023 05:34:13 PDT (-0700), geert@xxxxxxxxxxxxxx wrote:
Hi Prabhakar,
On Fri, Sep 29, 2023 at 2:07 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Enable the configs required by the below IP blocks which are
present on RZ/Five SoC:
* ADC
* CANFD
* DMAC
* eMMC/SDHI
* OSTM
* RAVB (+ Micrel PHY)
* RIIC
* RSPI
* SSI (Sound+WM8978 codec)
* Thermal
* USB (PHY/RESET/OTG)
Along with the above some core configs are enabled too,
-> CPU frequency scaling as RZ/Five does support this.
-> MTD is enabled as RSPI can be connected to flash chips
-> Enabled I2C chardev so that it enables userspace to read/write
i2c devices (similar to arm64)
-> Thermal configs as RZ/Five SoC does have thermal unit
-> GPIO regulator as we might have IP blocks for which voltage
levels are controlled by GPIOs
-> OTG configs as RZ/Five USB can support host/function
-> Gadget configs so that we can test USB function (as done in arm64
all the gadget configs are enabled)
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
As I expect this to go in through the RISC-V tree, I will let the
RISC-V people handle any discussion about more options that should be
made modular instead of builtin.
I'm pretty much agnostic on that front, so I'm cool just picking up
this. I've got just patch 5 in my queue for testing, there's a few
other things in front of it but it should show up on for-next soon.
Gr{oetje,eeting}s,
Geert
