On Tue, Oct 3, 2023 at 11:48 AM Geert Uytterhoeven
<geert+renesas@xxxxxxxxx> wrote:
>
> The unit address in the example does not match the reg property.
> Correct the unit address to match reality.
>
> Fixes: 3e7bf4685e42786d ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Cheers,
Prabhakar
> diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> index 9ab5f0c435d4df16..d2cbe49f4e15fdc4 100644
> --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> @@ -69,7 +69,7 @@ examples:
> - |
> #include <dt-bindings/interrupt-controller/irq.h>
>
> - cache-controller@2010000 {
> + cache-controller@13400000 {
> compatible = "andestech,ax45mp-cache", "cache";
> reg = <0x13400000 0x100000>;
> interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.34.1
>
