Hi Linus Walleij,
Thanks for the feedback.
> Subject: Re: [PATCH 2/2] pinctrl: renesas: rzg2l: Enable noise filter for
> GPIO interrupt input
>
> On Mon, Sep 18, 2023 at 2:34 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
>
> > As per RZ/G2L hardware manual Rev.1.30 section 8.7.3 GPIO Interrupt
> > (TINT) and 41.4.1 Operation for GPIO function, we need to set digital
> > noise filter for GPIO interrupt.
> >
> > This patch enables noise filter for GPIO interrupt in
> > rzg2l_gpio_irq_enable() and disable it in rzg2l_gpio_irq_disable().
> >
> > Fixes: db2e5f21a48e ("pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain
> > to handle GPIO interrupt")
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > Tested-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> Why is this called "digital noise filter" when the rest of the world calls
> it "debounce"? It is a bit confusing to have differing terminology in the
> kernel.
>
> (There might be a good reason, such that the noise in question is very
> different from mechanical button bounce noise.)
It is almost same.
>
> Is this only applicable to interrupt lines or also to GPIO lines in
> general? Because I just want to ascertain that in that case the existing
> binding for @PIN_CONFIG_INPUT_DEBOUNCE and the corresponding backend call
> from gpio_chip() maps to the same feature as well.
>
> It seems hard-coded for some pins in the Renesas driver right now but the
> day you make this configurable from DT please call it debounce, if the
> usecase is similar.
Yes, the usecase is similar and we can use PIN_CONFIG_INPUT_DEBOUNCE
for enabling digital noise filter.
But apart from this, I need to add 2 more configurable properties
associated with DT for PIN_CONFIG_INPUT_DEBOUNCE.
1) Digital Noise Filter Number Register (FILNUM)
This register sets the number of FF stages of digital noise filter for GPIO pin and NMI pin.
00b: 4-stage filter (41.666 ns x 4 = 166.666 ns) (initial value)
01b: 8-stage filter (41.666 ns x 8 = 333.333 ns)
10b: 12-stage filter (41.666 ns x 12 = 500 ns)
11b: 16-stage filter (41.666 ns x 16 = 666.666 ns)
Note: This value is the value when the external clock is 24MHz.
2) Digital Noise Filter Clock Selection Register (FILCLKSEL):
The FILCLKSEL register selects the divided clock to be input to digital noise filters.
00b: Not divided (initial value)
01b: Divided by 9000 (41.666 ns x 9000 = 375,000 ns)
10b: Divided by 18000 (41.666 ns x 18000 = 750,000 ns)
11b: Divided by 36000 (41.666 ns x 36000 = 1,500,000 ns)
Note: This value is the value when the external clock is 24MHz.
Q1) What is the recommended way to associate the above values with
PIN_CONFIG_INPUT_DEBOUNCE?
Eg: I need to configure filter on, 8 stage filter , a divisor of 18000 for a mechanical button bounce noise.
Cheers,
Biju
