The clock dividers x 1/1 and x 1/2 might be used with clock stop bit
enabled or not. While this table contains the enabled flavor (STPnHCK == 0).
The version for stopped clock (STPnHCK == 1) is missing. This might
result in warnings like [1] because no valid clock divider is found.
Resulting in a 0 divider.
There are Renesas ARM Trusted Firmware version out there which e.g.
configure 0x201 (shifted logical right by 2: 0x80) and with this match
the added { STPnHCK | 0, 1 }:
https://github.com/renesas-rcar/arm-trusted-firmware/blob/rcar_gen3_v2.3/drivers/renesas/rcar/emmc/emmc_init.c#L108
[1]
------------[ cut here ]------------
sd1h: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:141 divider_recalc_rate+0x48/0x70
Modules linked in:
CPU: 1 PID: 1 Comm: swapper/0 Not tainted 6.1.52 #1
Hardware name: Custom board based on r8a7796 (DT)
pstate: 40000005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : divider_recalc_rate+0x48/0x70
lr : divider_recalc_rate+0x48/0x70
sp : ffff800008033820
x29: ffff800008033820 x28: 0000000000000000 x27: 0000000000000001
x26: ffff80000894c19f x25: 0000000000000000 x24: ffff800008033958
x23: ffff0004402fc4a8 x22: ffff0004402fc400 x21: ffff0004402f8400
x20: 0000000000000000 x19: 000000002fadcf80 x18: ffff80000875c290
x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000
x14: fffffffffffc0000 x13: 0a74657320746f6e x12: 204f52455a5f574f
x11: 4c4c415f52454449 x10: 5649445f4b4c4320 x9 : 00080000000000ff
x8 : 0000000000000003 x7 : ffff800008034000 x6 : ffff800008030000
x5 : ffff000440188000 x4 : ffff800008034000 x3 : 0000000000000001
x2 : 2836f9a35ff96400 x1 : 2836f9a35ff96400 x0 : 0000000000000000
Call trace:
divider_recalc_rate+0x48/0x70
clk_divider_recalc_rate+0x48/0x50
__clk_register+0x450/0x5d0
clk_hw_register+0x28/0x40
__clk_hw_register_divider+0x148/0x18c
clk_register_divider_table+0x48/0x60
cpg_sdh_clk_register+0x88/0xd0
rcar_gen3_cpg_clk_register+0x168/0x490
cpg_mssr_register_core_clk+0x16c/0x1c0
cpg_mssr_probe+0x128/0x280
platform_probe+0x64/0xb0
really_probe+0x148/0x278
__driver_probe_device+0xec/0x104
driver_probe_device+0x38/0xf0
__driver_attach+0x4c/0xfc
bus_for_each_dev+0x78/0xbc
driver_attach+0x20/0x28
bus_add_driver+0x17c/0x1d0
driver_register+0xac/0xe8
__platform_driver_probe+0x88/0xe0
cpg_mssr_init+0x20/0x28
do_one_initcall+0x88/0x1c8
kernel_init_freeable+0x2b0/0x2b8
kernel_init+0x20/0x124
ret_from_fork+0x10/0x20
---[ end trace 0000000000000000 ]---
------------[ cut here ]------------
Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling")
CC: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
CC: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Signed-off-by: Dirk Behme <dirk.behme@xxxxxxxxxxxx>
---
drivers/clk/renesas/rcar-cpg-lib.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c
index e2e0447de190..4d6271714755 100644
--- a/drivers/clk/renesas/rcar-cpg-lib.c
+++ b/drivers/clk/renesas/rcar-cpg-lib.c
@@ -70,8 +70,8 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
#define STPnHCK BIT(9 - SDnSRCFC_SHIFT)
static const struct clk_div_table cpg_sdh_div_table[] = {
- { 0, 1 }, { 1, 2 }, { STPnHCK | 2, 4 }, { STPnHCK | 3, 8 },
- { STPnHCK | 4, 16 }, { 0, 0 },
+ { 0, 1 }, { 1, 2 }, { STPnHCK | 0, 1 }, { STPnHCK | 1, 2 },
+ { STPnHCK | 2, 4 }, { STPnHCK | 3, 8 }, { STPnHCK | 4, 16 }, { 0, 0 },
};
struct clk * __init cpg_sdh_clk_register(const char *name,
--
2.28.0
