Quoting Biju Das (2023-08-24 03:48:11) > According to Table 3. ("Output Source") in the 5P35023 datasheet, > the output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3, > 4=DIFF1, 5=DIFF2. But the code uses inverse. Fix this mapping issue. > > Suggested-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > Closes: https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0Y2ZpLCMNg@xxxxxxxxxxxxxx/ > Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver") > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > --- Applied to clk-fixes