RE: [PATCH v3 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes

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Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Monday, September 4, 2023 5:48 PM
> 
> Hi Shimoda-san,
> 
> On Fri, Sep 1, 2023 at 3:27 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > Add PCIe Host and Endpoint nodes for R-Car S4-8 (R8A779F0).
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> 
> Thanks for your patch!

Thank you for your review!

> > --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> > @@ -711,6 +725,124 @@ hscif3: serial@e66a0000 {
> >                         status = "disabled";
> >                 };
> >
> > +               pciec0: pcie@e65d0000 {
> > +                       compatible = "renesas,r8a779f0-pcie",
> > +                                    "renesas,rcar-gen4-pcie";
> > +                       reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
> > +                             <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
> > +                             <0 0xe65d6200 0 0x1100>, <0 0xe65d7000 0 0x0400>,
> 
> s/0x1100/0x0e00/

Oops. I'll fix it on v4.

> > +                             <0 0xfe000000 0 0x400000>;
> > +                       reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
> > +                       interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "msi", "dma", "sft_ce", "app";
> > +                       clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
> > +                       clock-names = "core", "ref";
> > +                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> > +                       resets = <&cpg 624>;
> > +                       reset-names = "pwr";
> > +                       max-link-speed = <4>;
> > +                       num-lanes = <2>;
> > +                       #address-cells = <3>;
> > +                       #size-cells = <2>;
> > +                       bus-range = <0x00 0xff>;
> > +                       device_type = "pci";
> > +                       ranges = <0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>;
> 
> The binding example has one extra line, and uses 0x02000000 instead
> of 0x82000000.
> 
> Which one is correct/complete?

The binding example is correct/complete because Manivannan asked me about the first argument on v13
and I revised the bindings:

https://lore.kernel.org/linux-pci/TYBPR01MB53414D9435EFA3C5546E4D19D8679@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/


> > +                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
> 
> My comments above apply to the other channel, too.

I got it. I'll fix them on v4.

Best regards,
Yoshihiro Shimoda

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds




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