Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@xxxxxxxxxxxx>:
On Fri, 18 Aug 2023 14:57:17 +0100 you wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Hi All,
>
> non-coherent DMA support for AX45MP
> ====================================
>
> [...]
Here is the summary with links:
- [v12,1/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list
https://git.kernel.org/riscv/c/93e0e2419b65
- [v12,2/6] riscv: errata: Add Andes alternative ports
https://git.kernel.org/riscv/c/f2863f30d1b0
- [v12,3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support
https://git.kernel.org/riscv/c/30bc090f40f8
- [v12,4/6] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller
https://git.kernel.org/riscv/c/555dd72bc06e
- [v12,5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core
https://git.kernel.org/riscv/c/f508b0175578
- [v12,6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
https://git.kernel.org/riscv/c/ed1a8872ff83
You are awesome, thank you!
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