Hi Biju,
On Thu, Aug 24, 2023 at 11:20 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > Subject: Re: [PATCH v4 3/4] clk: vc3: Fix output clock mapping
> > On Thu, Aug 24, 2023 at 10:25 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > wrote:
> > > According to Table 3. ("Output Source") in the 5P35023 datasheet, the
> > > output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1,
> > > 5=DIFF2. But the code uses inverse. Fix this mapping issue.
> > >
> > > Suggested-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> > > Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver")
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> >
> > This order should be documented in the DT bindings, too.
>
> Ok, will update the mapping in bindings like below.
>
> + assigned-clocks:
> + items:
> + - description: Link clock generator.
> + - description: Output clock index. The index is mapped to the clock
> + output in the hardware manual as follows
> + 0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.
> +
There is no need to document assigned-clocks.
The clock indices documentation belongs to the #clock-cells property.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
