Hi Stephen Boyd,
Thanks for the feedback.
> Subject: Re: [PATCH v3 2/4] clk: vc3: Fix 64 by 64 division
>
> Quoting Biju Das (2023-08-17 07:22:09)
> > Fix the below cocci warnings by replacing do_div()->div64_ul() and
> > bound the result with a max value of U16_MAX.
> >
> > cocci warnings:
> > drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a
> > 64-by-32 division, please consider using div64_ul instead.
> >
> > Reported-by: Julia Lawall <julia.lawall@xxxxxxxx>
> > Closes:
> > Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver")
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > v2->v3:
> > * Added to this patch series.
> > v1->v2:
> > * Added fixes tag.
> > ---
> > drivers/clk/clk-versaclock3.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/clk-versaclock3.c
> > b/drivers/clk/clk-versaclock3.c index 7ab2447bd203..3ded616a0d15
> > 100644
> > --- a/drivers/clk/clk-versaclock3.c
> > +++ b/drivers/clk/clk-versaclock3.c
> > @@ -401,9 +401,8 @@ static long vc3_pll_round_rate(struct clk_hw *hw,
> unsigned long rate,
> > /* Determine best fractional part, which is 16 bit wide
> */
> > div_frc = rate % *parent_rate;
> > div_frc *= BIT(16) - 1;
> > - do_div(div_frc, *parent_rate);
> >
> > - vc3->div_frc = (u32)div_frc;
> > + vc3->div_frc = min_t(u64, div64_ul(div_frc,
> > + *parent_rate), U16_MAX);
> > rate = (*parent_rate *
> > (vc3->div_int * VC3_2_POW_16 + div_frc) /
> > VC3_2_POW_16);
>
> ^ Should this
> be vc3->div_frc now to get the clamped value? --|
Yes, it is clamped value. I will send next version fixing
this.
Cheers,
Biju
