Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v6 2/2] drivers: clk: Add support for versa3 clock
> driver
>
> Hi Biju,
>
> On Wed, Jul 5, 2023 at 7:10 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > Add support for Renesas versa3 clock driver(5p35023).
> > The clock generator provides 6 output clocks.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Thanks for your patch, which is now commit 6e9aff555db7b681 ("clk: Add
> support for versa3 clock driver") in clk/clk-next.
>
> > --- /dev/null
> > +++ b/drivers/clk/clk-versaclock3.c
>
> > +enum vc3_clk {
> > + VC3_DIFF2,
> > + VC3_DIFF1,
> > + VC3_SE3,
> > + VC3_SE2,
> > + VC3_SE1,
> > + VC3_REF,
> > +};
>
> The bindings do not mention the mapping from clock indices to actual
> outputs. According to Table 3. ("Output Source") in the 5P35023
> datasheet, I would expect the mapping to be 0=REF, 1=SE1, 2=SE2, 3=SE3,
> 4=DIFF1, 5=DIFF2. But the above uses the order in the Block Diagram,
> which is the inverse...
I didn't give much attention to the mapping. Yes, as you say mapping should
be based on Table 3. ("Output Source") in the 5P35023
datasheet and the tool output[1] are also in line with this table.
I will send follow up binding/driver patches to correct the same.
[1]
https://i2.paste.pics/a253ce7cdc8720c3b5eb6953b97b25ff.png
Cheers,
Biju
