Hi Fabrizio,
Thanks for your patch!
On Thu, Jun 22, 2023 at 1:34 PM Fabrizio Castro
<fabrizio.castro.jz@xxxxxxxxxxx> wrote:
> The Renesas RZ/V2M SoC comes with 6 CSI IPs (CSI0, CSI1, CSI2
> CSI3, CSI4, and CSI5), however Linux is only allowed control
> of CSI0 and CSI4.
> CSI0 shares its reset and PCLK lines with CSI1, CSI2, and CSI3.
> CSI4 shares its reset and PCLK lines with CSI5.
That sounds like a marvelous idea.... :-(
> This commit adds support for the relevant clocks.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> ---
>
> v2: no changes
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-for-v6.6.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
