Hello Serge, > From: Serge Semin, Sent: Monday, June 5, 2023 8:16 PM > > On Wed, May 10, 2023 at 03:22:25PM +0900, Yoshihiro Shimoda wrote: > > Renesas R-Car Gen4 PCIe controllers have an unexpected register value on > > the dbi+0x97b register. So, add a new capability flag "EDMA_UNROLL" > > which would force the unrolled eDMA mapping for the problematic > > device, > > > as suggested by Serge Semin. > > Drop this. Suggested-by tag already means that. I got it. > > > > Suggested-by: Serge Semin <fancer.lancer@xxxxxxxxx> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> > > --- > > drivers/pci/controller/dwc/pcie-designware.c | 8 +++++++- > > drivers/pci/controller/dwc/pcie-designware.h | 5 +++-- > > 2 files changed, 10 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index 8b2978c6eb23..e405bfae0191 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -881,8 +881,14 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) > > * Indirect eDMA CSRs access has been completely removed since v5.40a > > * thus no space is now reserved for the eDMA channels viewport and > > * former DMA CTRL register is no longer fixed to FFs. > > + * > > + * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason > > > + * may have zeros in the eDMA CTRL register even though the HW-manual > > s/may have/have I'll fix it. > (your comment is about a particular device which for sure has the > denoted problem.) I understood it. > Other than that the change looks good. Thanks! > Reviewed-by: Serge Semin <fancer.lancer@xxxxxxxxx> Thank you very much for your review! Best regards, Yoshihiro Shimoda > -Serge(y) > > > + * explicitly states there must FFs if the unrolled mapping is enabled. > > + * For such cases the low-level drivers are supposed to manually > > + * activate the unrolled mapping to bypass the auto-detection procedure. > > */ > > - if (dw_pcie_ver_is_ge(pci, 540A)) > > + if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) > > val = 0xFFFFFFFF; > > else > > val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > index 06e044e2163a..2639206b4c18 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > @@ -54,8 +54,9 @@ > > > > /* DWC PCIe controller capabilities */ > > #define DW_PCIE_CAP_REQ_RES 0 > > -#define DW_PCIE_CAP_IATU_UNROLL 1 > > -#define DW_PCIE_CAP_CDM_CHECK 2 > > +#define DW_PCIE_CAP_EDMA_UNROLL 1 > > +#define DW_PCIE_CAP_IATU_UNROLL 2 > > +#define DW_PCIE_CAP_CDM_CHECK 3 > > > > #define dw_pcie_cap_is(_pci, _cap) \ > > test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) > > -- > > 2.25.1 > >
