On Wed, May 10, 2023 at 03:22:30PM +0900, Yoshihiro Shimoda wrote: > Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0) > PCIe endpoint module. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Reviewed-by: Serge Semin <fancer.lancer@xxxxxxxxx> > Acked-by: Manivannan Sadhasivam <mani@xxxxxxxxxx> > --- > .../bindings/pci/rcar-gen4-pci-ep.yaml | 98 +++++++++++++++++++ > 1 file changed, 98 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml > > diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml > new file mode 100644 > index 000000000000..0453bdcf9645 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml > @@ -0,0 +1,98 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2022-2023 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas R-Car Gen4 PCIe Endpoint > + > +maintainers: > + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> > + > +allOf: > + - $ref: snps,dw-pcie-ep.yaml# > + > +properties: > + compatible: > + items: > + - const: renesas,r8a779f0-pcie-ep # R-Car S4-8 > + - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4 > + > + reg: > + maxItems: 6 > + > + reg-names: > + items: > + - const: dbi > + - const: dbi2 > + - const: atu > + - const: dma > + - const: app > + - const: addr_space > + > + interrupts: > + maxItems: 3 > + > + interrupt-names: > + items: > + - const: dma > + - const: sft_ce > + - const: app > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + max-functions: > + maximum: 2 > + > + max-link-speed: > + maximum: 4 > + > + num-lanes: > + maximum: 4 > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - resets > + - power-domains > + - clocks > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/r8a779f0-sysc.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie0_ep: pcie-ep@e65d0000 { > + compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep"; > + reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2800 0 0x0800>, > + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, > + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>; > + reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space"; Just figured this out. I see you defining the dbi2 as <0 0xe65d2800 0 0x0800>. But sometime before you mentioned that your device has the next CSRs layout: ! +0x0000 : Function 0 (common address in Root complex and Endpoint mode) +0x1000 : Function 1 (Endpoint mode only) +0x2000 : Shadow register for Function 0 ! +0x2800 : Shadow register for Function 1 it means you have the dbi space defined for both functions meanwhile the dbi2 space defined for _function #1_ only. Moreover your DW PCIe End-point driver disables the multi-function feature support. So AFAICS either you have wrong DW PCIe EP example node or the node is wrong in your platform DTS too and you have a malfunction end-point mode. Am I missing something? In any case based on the your End-point driver implementation dbi2 is supposed to be defined at the 0xe65d2000 base address. -Serge(y) > + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "dma", "sft_ce", "app"; > + clocks = <&cpg CPG_MOD 624>; > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > + resets = <&cpg 624>; > + num-lanes = <2>; > + max-link-speed = <4>; > + }; > + }; > -- > 2.25.1 >
