Hi Dan Carpenter, Thanks for the feedback. > -----Original Message----- > From: Dan Carpenter <error27@xxxxxxxxx> > Sent: Thursday, April 13, 2023 5:49 AM > To: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > Cc: oe-kbuild@xxxxxxxxxxxxxxx; Michael Turquette <mturquette@xxxxxxxxxxxx>; > Stephen Boyd <sboyd@xxxxxxxxxx>; lkp@xxxxxxxxx; oe-kbuild- > all@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; Geert Uytterhoeven > <geert+renesas@xxxxxxxxx>; Prabhakar Mahadev Lad <prabhakar.mahadev- > lad.rj@xxxxxxxxxxxxxx>; linux-renesas-soc@xxxxxxxxxxxxxxx > Subject: Re: [PATCH v4 2/3] drivers: clk: Add support for versa3 clock > driver > > The divide makes sense in context then... Thanks for the explanation. > > This check seemed like a useful thing and found a couple bugs but it turns > out that condition divides can be the most readable thing in context. So it > maybe has a too high false positive rate. >From the execution point of view the code suggested by you is faster. So I would like to use that. For readability point. I will put a comment like below in next version. /* The below check is equivalent to req->best_parent_rate / req->rate */ if (req->best_parent_rate >= req->rate) Apart from this I need to send some change in next version based on [1], as some of mux missing determine_rate. [1] https://lore.kernel.org/linux-renesas-soc/20221018-clk-range-checks-fixes-v3-0-9a1358472d52@xxxxxxxxxx/T/#t Cheers, Biju
