Add vspd node to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
v1->v2:
* Added Rb tag from Geert.
* Reorder the patch based on the module fcpvd, vspd and then DSI
for both RZ/G2L and RZ/V2L.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index e90c517077ab..7698752742df 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -618,6 +618,19 @@ sbc: spi@10060000 {
status = "disabled";
};
+ vspd: vsp@10870000 {
+ compatible = "renesas,r9a07g044-vsp2";
+ reg = <0 0x10870000 0 0x10000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_LCDC_RESET_N>;
+ renesas,fcp = <&fcpvd>;
+ };
+
fcpvd: fcp@10880000 {
compatible = "renesas,r9a07g044-fcpvd",
"renesas,fcpv";
--
2.25.1
