Add fcpvd node to RZ/V2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
v1->v2:
* Added Rb tag from Geert.
* Reorder the patch based on the module fcpvd, vspd and then DSI
for both RZ/G2L and RZ/V2L.
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 304ade54425b..9001673a9e3c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -623,6 +623,18 @@ sbc: spi@10060000 {
status = "disabled";
};
+ fcpvd: fcp@10880000 {
+ compatible = "renesas,r9a07g054-fcpvd",
+ "renesas,fcpv";
+ reg = <0 0x10880000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
+ <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
+ <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_LCDC_RESET_N>;
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g054-cpg";
reg = <0 0x11010000 0 0x10000>;
--
2.25.1
