On Fri, Mar 31, 2023 at 11:37:30AM +0100, Lad, Prabhakar wrote: > > As far as I recall, the #else path here was needed previously > > to work around a binutils dependency, but with the current > > code, it should be possible to just always enable > > CONFIG_RISCV_ISA_ZICBOM when RISCV_DMA_NONCOHERENT is used. > > > Are you suggesting something like below? > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 4dadf35ac721..a55dee98ccf8 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -242,6 +242,7 @@ config RISCV_DMA_NONCOHERENT > select ARCH_HAS_SYNC_DMA_FOR_CPU > select ARCH_HAS_SYNC_DMA_FOR_DEVICE > select DMA_DIRECT_REMAP > + select RISCV_ISA_ZICBOM > > config AS_HAS_INSN > def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) > t0$(comma) t0$(comma) zero) > @@ -465,7 +466,6 @@ config RISCV_ISA_ZICBOM > depends on MMU > depends on RISCV_ALTERNATIVE > default y > - select RISCV_DMA_NONCOHERENT > help > Adds support to dynamically detect the presence of the ZICBOM > extension (Cache Block Management Operations) and enable its > Does that actually work? I don't think it does. If you try to enable RISCV_ISA_ZICBOM then you won't get RISC_DMA_NONCOHERENT turned on. Run menuconfig and disable support for Renesas, SiFive and T-Head SoCs & you can replicate. I think one of RISCV_ISA_ZICBOM and RISCV_DMA_NONCOHERENT should just be dropped, although I don't know which one to pick! Making RISCV_DMA_NONCOHERENT user selectable probably makes the most sense.
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