Hi Stephen,
Thanks for the feedback.
> Subject: RE: [PATCH v2 2/3] drivers: clk: Add support for versa3 clock
> driver
>
> Quoting Biju Das (2023-03-28 11:07:59)
> >
> > Stream parameters are [ 35.051544] ###### vc3_clk_out_round_rate
> rate=12288000
> > 48000Hz, S16_LE,[ 35.051590] ###### vc3_clk_out_round_rate rate=12288000
> > 2 channels
> > Using 16 oc[ 35.058206] ###### vc3_clk_out_recalc_rate
> parent_rate=12287998
> > taves of pink noise
> > Rate set to 48000Hz (requested 48000Hz)
> >
> > Note:
> > I have tried taking out clk_ops and replaced below calls in
> > vc3_of_clk_get(),
> >
> > The clk mux doesn't get callbacks during playback to change the rates.
> >
> > if (idx == VC3_REF)
> > hw = devm_clk_hw_register_fixed_factor(dev, name, "xtal",
> >
> CLK_SET_RATE_PARENT, 1, 1);
> > else
> > hw = devm_clk_hw_register_fixed_factor_parent_hw(dev,
> name, &clk_mux[idx].hw,
> >
> > CLK_SET_RATE_PARENT, 1, 1);
>
> Does the clk that is a child of the fixed factor 1/1 clk also have
> CLK_SET_RATE_PARENT flag set?
There is no child for fixed factor 1/1 clk. I just dropped clk-fops and
Used fixed factor 1/1 for output clks and all parents of the output clks is
have CLK_SET_RATE_PARENT flag set.
diff2-mux is parent of fixed factor 1/1 "diff2" output clk
diff1-mux is parent of fixed factor 1/1 "diff1" output clk
se3-mux is parent of fixed factor 1/1 "se3" output clk
se2-mux is parent of fixed factor 1/1 "se2" output clk
se1-mux is parent of fixed factor 1/1 "se1" output clk
xtal is parent of fixed factor 1/1 "ref" output clk
static struct vc3_hw_data clk_mux[] = {
[VC3_DIFF2_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_DIFF2_CTRL_REG,
.bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "diff2_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV1].hw,
&clk_div[VC3_DIV3].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_DIFF1_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_DIFF1_CTRL_REG,
.bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "diff1_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV1].hw,
&clk_div[VC3_DIV3].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_SE3_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE3_DIFF1_CTRL_REG,
.bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "se3_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV2].hw,
&clk_div[VC3_DIV4].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_SE2_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE2_CTRL_REG0,
.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "se2_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV5].hw,
&clk_div[VC3_DIV4].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_SE1_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE1_DIV4_CTRL,
.bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
},
.hw.init = &(struct clk_init_data){
.name = "se1_mux",
.ops = &vc3_clk_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&clk_div[VC3_DIV5].hw,
&clk_div[VC3_DIV4].hw
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
}
};
xtal 0 0 0 24000000 0 0 50000 Y
ref 0 0 0 24000000 0 0 50000 Y
pfd1 0 0 0 24000000 0 0 50000 Y
pll1 0 0 0 600000000 0 0 50000 Y
div2 0 0 0 12000000 0 0 50000 Y
se3_mux 0 0 0 12000000 0 0 50000 Y
se3 0 0 0 12000000 0 0 50000 Y
div1_mux 0 0 0 600000000 0 0 50000 Y
div1 0 0 0 25000000 0 0 50000 Y
diff1_mux 0 0 0 25000000 0 0 50000 Y
diff1 0 0 0 25000000 0 0 50000 Y
pfd3_mux 0 0 0 24000000 0 0 50000 Y
pfd3 0 0 0 960000 0 0 50000 Y
pll3 0 0 0 564480000 0 0 50000 Y
div5 0 0 0 11289600 0 0 50000 Y
se1_mux 0 0 0 11289600 0 0 50000 Y
se1 0 0 0 11289600 0 0 50000 Y
se2_mux 0 0 0 11289600 0 0 50000 Y
se2 0 0 0 11289600 0 0 50000 Y
pfd2_mux 0 0 0 24000000 0 0 50000 Y
pfd2 0 0 0 24000000 0 0 50000 Y
pll2 0 0 0 491519897 0 0 50000 Y
div4_mux 0 0 0 491519897 0 0 50000 Y
div4 0 0 0 12287998 0 0 50000 Y
div3_mux 0 0 0 491519897 0 0 50000 Y
div3 0 0 0 12287998 0 0 50000 Y
diff2_mux 0 0 0 12287998 0 0 50000 Y
diff2 0 0 0 12287998 0 0 50000 Y
Cheers,
Biju
