Add device nodes for the PCI Express controller and the related
external PCIe bus clock on the Renesas R-Car H1 (R8A7779) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
Comparing this to R-Car Gen2 SoCs (r8a779[01].dtsi), the latter have an
extra dma-ranges entry:
<0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>
However, R-Car Gen2 supports LPAE, while R-Car H1 does not.
Does this need an entry with 0x43000000? After +25 years of exposue, I
still can't say I understand the PCI DT bindings...
---
arch/arm/boot/dts/r8a7779.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 97b767d81d926049..bba0c6d2386cd042 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -563,6 +563,13 @@ extal_clk: extal {
clock-frequency = <0>;
};
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie-bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@@ -699,6 +706,31 @@ R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
};
};
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7779";
+ reg = <0xfe000000 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x20000000 0x20000000 0 0x20000000>,
+ <0x42000000 0 0xc0000000 0xc0000000 0 0x20000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7779_CLK_PCIE>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0xff000044 4>;
--
2.34.1
