On 09/03/2023 08:57, Biju Das wrote: >>> It is clk generator HW specific. Clk generator is vital component >>> which provides clocks to the system. >> >> Every clock controller is vital... >> >>> We are providing some hardware feature which is exposed as dt >>> properties. >>> >>> Like clock output is fixed rate clock or dynamic rate clock/ >> >> OK, I wait then for proper description which will explain and justify this. > > Here it is, Please let me know is it ok? > > renesas,output-clock-fixed-rate-mode: > type: boolean > description: > In output clock fixed rate mode, the output clock frequency is always > fixed and the hardware will use the values from the OTP or full register > map initialized during boot. > If not given, the output clock rate is not fixed. > maxItems: 6 boolean is scalar, not array, so no maxItems. If the frequency is taken from OTP or register map, why they cannot also provide information the clock is fixed? > > Cheers, > Biju Best regards, Krzysztof
