Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH RFC 1/3] dt-bindings: clock: Add Renesas versa3 clock > generator bindings > > Hi Biju, > > On Wed, Mar 8, 2023 at 3:39 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote: > > > From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> On > > > 20/02/2023 14:13, Biju Das wrote: > > > > Document Renesas versa3 clock generator(5P35023) bindings. > > > > > > > > The 5P35023 is a VersaClock programmable clock generator and is > > > > designed for low-power, consumer, and high-performance PCI Express > > > > applications. The 5P35023 device is a three PLL architecture > > > > design, and each PLL is individually programmable and allowing for > > > > up to 6 unique frequency outputs. > > > > > > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/clock/renesas,versaclock3. > > > > +++ yaml > > > > > + clock-names: > > > > + oneOf: > > > > + - items: > > > > + - const: x1 > > > > + - items: > > > > + - const: clkin > > > > > > This should be specific, not one or another. Why do you have two > > > entirely different clock inputs? > > > > Reference input can be Crystal oscillator interface input(x1) or > > differential clock input pin(clkin) > > I believe that's purely a hardware feature, which does not need any software > configuration? > I.e. logically, there's just a single clock input, i.e. no need for clock- > names. OK. Agreed. Will remove clock-names. Cheers, Biju
