Hi Niklas,
On Sat, Feb 11, 2023 at 3:37 PM Niklas Söderlund
<niklas.soderlund+renesas@xxxxxxxxxxxx> wrote:
> Add the CSI core clock and the CSI40 and CSI41 module clocks, which are
> used by the CSI-2 Interfaces on the Renesas R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -146,6 +146,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
> DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
> DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
> DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
> + DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
> DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
> DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
>
> @@ -164,7 +165,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
> DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
> DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
> + DEF_MOD("csi40", 331, R8A779G0_CLK_CSI),
I will move this one one line down while applying, to preserve sort order.
> DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
> + DEF_MOD("csi41", 400, R8A779G0_CLK_CSI),
> DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
> DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
> DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-for-v6.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
