Hi Geert, > > Documentation says only DTDL of 200 is allowed for this SoC. > > Do you have a pointer to that? Yes: Gen3 docs Rev.2.30 from Aug 2021, Section 59.2.1, Bits 22-20: "[R-Car H3, R-Car H3-N] 010: 2-clock-cycle delay Other than above: Setting prohibited" > We already have "renesas,dtdl" to configure this from DT. > Iff this is really needed, perhaps it should be added to r8a77951.dtsi? I have to disagree here. The docs say that other values are prohibited. IMO the driver should take care of valid values then. We should not rely on user provided input. > I suspect this is a leftover in the BSP from attempts to get MSIOF > working on R-Car H3 ES1.0 (which it never did for me, as CLK starts > and stops too soon, compared to MOSI/MISO). > On R-Car H3 ES2.0, everything works fine, without touching DTDL. The BSP originally has this patch for ES3 only. I extended to ES2 as well because that is what the docs say. Happy hacking, Wolfram
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