"Hi Wolfram,
On Wed, Jan 18, 2023 at 12:38 PM Wolfram Sang
<wsa+renesas@xxxxxxxxxxxxxxxxxxxx> wrote:
> From: Cong Dang <cong.dang.xn@xxxxxxxxxxx>
>
> According to the datasheets, the Strobe Timing Adjustment bit (STRTIM)
> setting is different on R-Car SoCs, i.e.
>
> R-Car H3 ES1.* : STRTIM[2:0] is set to 0x0
> R-Car M3 ES1.* : STRTIM[2:0] is set to 0x6
> other R-Car Gen3: STRTIM[2:0] is set to 0x7
> other R-Car Gen4: STRTIM[3:0] is set to 0xf
>
> To fix this issue, a DT match data was added to specify the setting
> for special use cases.
>
> Signed-off-by: Cong Dang <cong.dang.xn@xxxxxxxxxxx>
> Signed-off-by: Hai Pham <hai.pham.ud@xxxxxxxxxxx>
> [wsa: rebased, restructured a little, added Gen4 support]
> Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> ---
>
> Change since V1:
>
> * use proper mask when updating STRTIM bits (thanks, Geert!)
Thanks for the update!
> --- a/drivers/memory/renesas-rpc-if.c
> +++ b/drivers/memory/renesas-rpc-if.c
> @@ -163,6 +165,36 @@ static const struct regmap_access_table rpcif_volatile_table = {
> .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
> };
>
> +static const struct rpcif_info rpcif_info_r8a7795_es1 = {
> + .type = RPCIF_RCAR_GEN3,
> + .strtim = 0,
> +};
> +
> +static const struct rpcif_info rpcif_info_r8a7796_es1 = {
> + .type = RPCIF_RCAR_GEN3,
> + .strtim = 6,
> +};
> +
> +static const struct rpcif_info rpcif_info_gen3 = {
> + .type = RPCIF_RCAR_GEN3,
> + .strtim = 7,
> +};
> +
> +static const struct rpcif_info rpcif_info_rz_g2l = {
> + .type = RPCIF_RZ_G2L,
> + .strtim = 7,
> +};
> +
> +static const struct rpcif_info rpcif_info_gen4 = {
> + .type = RPCIF_RCAR_GEN4,
> + .strtim = 15,
> +};
> +
> +static const struct soc_device_attribute rpcif_info_match[] = {
> + { .soc_id = "r8a7795", .revision = "ES1.*", .data = &rpcif_info_r8a7795_es1 },
> + { .soc_id = "r8a7796", .revision = "ES1.*", .data = &rpcif_info_r8a7796_es1 },
As we do have a separate compatible value for R-Car M3-W+ aka R-Car M3-W ES3.0
("renesas,r8a77961-rpc-if"), and there is no R-Car M3-W ES2.x (see the PRR
screwup handling in renesas_soc_init()), you can just match against
"renesas,r8a7796-rpc-if instead.
> + { /* Sentinel. */ }
> +};
>
> /*
> * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
> @@ -321,12 +360,10 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
> /* DMA Transfer is not supported */
> regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0);
>
> - if (rpc->type == RPCIF_RCAR_GEN3)
> - regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
> - RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7));:q
> - else if (rpc->type == RPCIF_RCAR_GEN4)
> - regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
> - RPCIF_PHYCNT_STRTIM(15), RPCIF_PHYCNT_STRTIM(15));
> + regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
> + /* create mask with all affected bits set */
> + RPCIF_PHYCNT_STRTIM(BIT(fls(rpc->info->strtim)) - 1),
fls(0) = 0, and BIT(-1) is undefined, so this won't work for R-Car
H3 ES1.x. So I'm afraid you cannot handle this without storing the
actual mask ;-)
However, that issue will be moot as soon as we drop upstream support
for R-Car H3 ES1.x. I cannot test RPC on R-Car H3 ES1.x anyway, as
the RPC is locked by TF/A, and the firmware cannot be upgraded easily
due to lack of upstream TF/A support for R-Car H3 ES1.x
> + RPCIF_PHYCNT_STRTIM(rpc->info->strtim));
>
> regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3),
> RPCIF_PHYOFFSET1_DDRTMG(3));
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
