Hi Geert, Thanks for the feedback. On Mon, Jan 9, 2023 at 12:15 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Sat, Jan 7, 2023 at 9:47 PM Lad, Prabhakar > <prabhakar.csengg@xxxxxxxxx> wrote: > > On Fri, Jan 6, 2023 at 9:53 PM Conor Dooley <conor@xxxxxxxxxx> wrote: > > > On Fri, Jan 06, 2023 at 06:55:24PM +0000, Prabhakar wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > > > describes the L2 cache block. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > > > @@ -0,0 +1,81 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > +# Copyright (C) 2022 Renesas Electronics Corp. > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Andestech AX45MP L2 Cache Controller > > > > + > > > > +maintainers: > > > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > + > > > > +description: > > > > + A level-2 cache (L2C) is used to improve the system performance by providing > > > > + a large amount of cache line entries and reasonable access delays. The L2C > > > > + is shared between cores, and a non-inclusive non-exclusive policy is used. > > > > + > > > > +select: > > > > + properties: > > > > + compatible: > > > > + contains: > > > > + enum: > > > > + - andestech,ax45mp-cache > > > > + > > > > + required: > > > > + - compatible > > > > + > > > > +properties: > > > > + compatible: > > > > + items: > > > > + - const: andestech,ax45mp-cache > > > > + - const: cache > > > > > > You might find value in a specific compatible for your SoC & enforce > > > constraints for it. Or you might not & I don't care either way :) > > > > > Good point actually. Geert what do you think? > > That might be prudent, to cater for the way the standard AX45MP cache > block is integrated into the RZ/Five (or any other) SoC. > > Still, in the absence of an SoC-specific compatible value, you can > handle integration issues using soc_device_match(). > Agreed, I'll continue with the current DT bindings. Cheers, Prabhakar
