From: Phil Edworthy <phil.edworthy@xxxxxxxxxxx> Add SDHI/eMMC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx> --- This patch can clash with the below patch (which hasn't been reviewed yet): https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221212172804.1277751-2-biju.das.jz@xxxxxxxxxxxxxx/ drivers/clk/renesas/r9a09g011-cpg.c | 34 +++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index dd5e442ec4a9..8437b7d38e94 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -23,11 +23,14 @@ #define DIV_A DDIV_PACK(0x200, 0, 3) #define DIV_B DDIV_PACK(0x204, 0, 2) +#define DIV_D DDIV_PACK(0x204, 4, 2) #define DIV_E DDIV_PACK(0x204, 8, 1) #define DIV_W DDIV_PACK(0x328, 0, 3) #define SEL_B SEL_PLL_PACK(0x214, 0, 1) +#define SEL_D SEL_PLL_PACK(0x214, 1, 1) #define SEL_E SEL_PLL_PACK(0x214, 2, 1) +#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1) #define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1) enum clk_ids { @@ -50,11 +53,14 @@ enum clk_ids { CLK_PLL4, CLK_DIV_A, CLK_DIV_B, + CLK_DIV_D, CLK_DIV_E, CLK_DIV_W, CLK_SEL_B, CLK_SEL_B_D2, + CLK_SEL_D, CLK_SEL_E, + CLK_SEL_SDI, CLK_SEL_W0, /* Module Clocks */ @@ -81,6 +87,14 @@ static const struct clk_div_table dtable_divb[] = { {0, 0}, }; + +static const struct clk_div_table dtable_divd[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {0, 0}, +}; + static const struct clk_div_table dtable_divw[] = { {0, 6}, {1, 7}, @@ -94,8 +108,10 @@ static const struct clk_div_table dtable_divw[] = { /* Mux clock tables */ static const char * const sel_b[] = { ".main", ".divb" }; +static const char * const sel_d[] = { ".main", ".divd" }; static const char * const sel_e[] = { ".main", ".dive" }; static const char * const sel_w[] = { ".main", ".divw" }; +static const char * const sel_sdi[] = { ".main", ".pll2_200" }; static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { /* External Clock Inputs */ @@ -115,11 +131,14 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva), DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb), + DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd), DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL), DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw), DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b), + DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d), DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e), + DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi), DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w), DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2), @@ -128,6 +147,18 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2), DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), + DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0), + DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1), + DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2), + DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3), + DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4), + DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5), + DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6), + DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7), + DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8), + DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9), + DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10), + DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11), DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), @@ -151,6 +182,9 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), + DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6), + DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7), + DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8), -- 2.34.1
