Add device nodes for the pwm timer channels that are not assigned
to the ISP.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
v2->v3:
* Added Rb tag from Geert
v1->v2:
* Added resets property
---
arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 98 ++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 0373ec409d54..dcd3a05e54fe 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -135,6 +135,104 @@ sys: system-controller@a3f03000 {
reg = <0 0xa3f03000 0 0x400>;
};
+ pwm8: pwm@a4010400 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010400 0 0x80>;
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM8_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm9: pwm@a4010480 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010480 0 0x80>;
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM9_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm10: pwm@a4010500 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010500 0 0x80>;
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM10_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm11: pwm@a4010580 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010580 0 0x80>;
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM11_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm12: pwm@a4010600 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010600 0 0x80>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM12_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm13: pwm@a4010680 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010680 0 0x80>;
+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM13_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm14: pwm@a4010700 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010700 0 0x80>;
+ interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM14_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
i2c0: i2c@a4030000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
