On Thu, Nov 24, 2022 at 8:16 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Add PWM{8..14} clock and reset entries to CPG driver.
>
> The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has
> full control of channels 0 to 7, and channel 15, therefore Linux
> is only allowed to use channels 8 to 14.
>
> The PWM channel 15 shares apb clock and reset with PWM{8..14}.
> The reset is deasserted by the bootloader/ISP.
>
> Add PWM{8..14} clocks to CPG driver and mark apb clock as
> critical clock, so that the apb clock will be always on.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v1->v2:
> * Updated commit description
> * Replaced pwm8_15_pclk->cperi_grpf
> * Added reset entry R9A09G011_PWM_GPF_PRESETN
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-for-v6.3.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
