Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, November 30, 2022 1:53 AM
>
> According to the table in Note 5 for the OSC clock in Table 8.1.4e
> ("Lists of CPG clocks generated from PLL5") of the R-Car V4H Series
> Hardware User's Manual Rev. 0.54, the predividers for the OSC clock are
> 16 resp. 32 when using a 16.66 resp. 33.33 MHz external crystal.
>
> Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> ---
> To be queued in renesas-clk-for-v6.3.
>
> Presumably this was copied from r8a779f0-cpg-mssr.c, as R-Car S4-8 does
> support dividers of 15 and 19 with a 16.00 resp. 40.00 MHz external
> crystal.
I think so.
Best regards,
Yoshihiro Shimoda
> ---
> drivers/clk/renesas/r8a779g0-cpg-mssr.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> index 9863f1a51f4b36e2..2feb97fc37759267 100644
> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -212,20 +212,20 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
> * 14 13 (MHz)
> * ------------------------------------------------------------------------
> - * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /15
> + * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
> * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
> * 1 0 Prohibited setting
> - * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /38
> + * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
> */
> #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
> (((md) & BIT(13)) >> 13))
>
> static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
> /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div
> OSC prediv */
> - { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1,
> 15, },
> + { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1,
> 16, },
> { 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1,
> 19, },
> { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, },
> - { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1,
> 38, },
> + { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1,
> 32, },
> };
>
> static int __init r8a779g0_cpg_mssr_init(struct device *dev)
> --
> 2.25.1
