The following changes since commit b9a0be2054964026aa58966ce9724b672f210835:
arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts (2022-10-28 14:23:00 +0200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-riscv-dt-for-v6.2-tag1
for you to fetch changes up to 40005cb6093e92d24a1bdbc444311c25e4b28878:
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C (2022-11-17 20:27:02 +0100)
----------------------------------------------------------------
Renesas RISC-V DT updates for v6.2
- Add initial support for the Renesas RZ/Five SoC and the Renesas
RZ/Five SMARC EVK development board.
----------------------------------------------------------------
Lad Prabhakar (5):
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
MAINTAINERS: Add entry for Renesas RISC-V
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
MAINTAINERS | 3 +-
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 59 ++++++++++++++++++++
arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 47 ++++++++++++++++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 64 ++++++++++++++++++++++
7 files changed, 202 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
