> Subject: RE: [PATCH v10 2/2] pwm: Add support for RZ/G2L GPT
>
> Hi Geert,
>
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> > Sent: 08 November 2022 09:17
> > To: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > Cc: Thierry Reding <thierry.reding@xxxxxxxxx>; Philipp Zabel
> > <p.zabel@xxxxxxxxxxxxxx>; Uwe Kleine-König
> > <u.kleine-koenig@xxxxxxxxxxxxxx>; linux-pwm@xxxxxxxxxxxxxxx; Geert
> > Uytterhoeven <geert+renesas@xxxxxxxxx>; Chris Paterson
> > <Chris.Paterson2@xxxxxxxxxxx>; Biju Das <biju.das@xxxxxxxxxxxxxx>;
> > Prabhakar Mahadev Lad <prabhakar.mahadev- lad.rj@xxxxxxxxxxxxxx>;
> > linux-renesas-soc@xxxxxxxxxxxxxxx
> > Subject: Re: [PATCH v10 2/2] pwm: Add support for RZ/G2L GPT
> >
> > Hi Biju,
> >
> > On Mon, Nov 7, 2022 at 6:18 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit
> > > timer (GPT32E). It supports the following functions
> > > * 32 bits × 8 channels
> > > * Up-counting or down-counting (saw waves) or up/down-counting
> > > (triangle waves) for each counter.
> > > * Clock sources independently selectable for each channel
> > > * Two I/O pins per channel
> > > * Two output compare/input capture registers per channel
> > > * For the two output compare/input capture registers of each channel,
> > > four registers are provided as buffer registers and are capable of
> > > operating as comparison registers when buffering is not in use.
> > > * In output compare operation, buffer switching can be at crests or
> > > troughs, enabling the generation of laterally asymmetric PWM
> waveforms.
> > > * Registers for setting up frame cycles in each channel (with capability
> > > for generating interrupts at overflow or underflow)
> > > * Generation of dead times in PWM operation
> > > * Synchronous starting, stopping and clearing counters for arbitrary
> > > channels
> > > * Starting, stopping, clearing and up/down counters in response to input
> > > level comparison
> > > * Starting, clearing, stopping and up/down counters in response to a
> > > maximum of four external triggers
> > > * Output pin disable function by dead time error and detected
> > > short-circuits between output pins
> > > * A/D converter start triggers can be generated (GPT32E0 to
> > > GPT32E3)
> > > * Enables the noise filter for input capture and external trigger
> > > operation
> > >
> > > This patch adds basic pwm support for RZ/G2L GPT driver by creating
> > > separate logical channels for each IOs.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > ---
> > > v9->v10:
> > > * Updated the error handling in probe(), clk_disable_unprepare called
> > > on the error path.
> > > * Removed ch_en array and started using bitmask instead.
> >
> > Thanks for the update!
> >
> > > --- /dev/null
> > > +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> >
> > > +static int rzg2l_gpt_probe(struct platform_device *pdev) {
> > > + DECLARE_BITMAP(ch_en_bits, RZG2L_MAX_PWM_CHANNELS);
> >
> > [...]
> >
> > > + /*
> > > + * We need to keep the clock on, in case the bootloader has
> > enabled the
> > > + * PWM and is running during probe().
> > > + */
> > > + *ch_en_bits = 0;
> >
> > bitmap_zero(), which will be optimized to a single assignment.
>
> OK, Will do it in the next version. Whilst wait for other reviewers to give
> some feedback for the current patch set.
>
Will send V11 with this change.
Cheers,
Biju
