Hello: The following patches were marked "mainlined", because they were applied to geert/renesas-devel.git (master): Series: Add support for Renesas RZ/Five SoC Submitter: Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> Committer: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Patchwork: https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=689949 Lore link: https://lore.kernel.org/r/20221028165921.94487-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx Patches: [v5,1/7] dt-bindings: riscv: Sort the CPU core list alphabetically [v5,2/7] dt-bindings: riscv: Add Andes AX45MP core to the list [v5,3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option [v5,4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC [v5,5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK [v5,7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Series: [1/2] arm64: dts: renesas: r8a779f0: Add HSCIF 0+1 nodes Submitter: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> Patchwork: https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=649908 Lore link: https://lore.kernel.org/r/20220613131033.10053-1-wsa+renesas@xxxxxxxxxxxxxxxxxxxx Patches: [1/2] arm64: dts: renesas: r8a779f0: Add HSCIF 0+1 nodes [2/2] arm64: dts: renesas: spider-cpu: Switch from SCIF3 to HSCIF0 Series: Add support for Renesas RZ/Five SoC Submitter: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Committer: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Patchwork: https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=667677 Lore link: https://lore.kernel.org/r/20220815151451.23293-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx Patches: [v2,1/8] dt-bindings: riscv: Sort the CPU core list alphabetically [v2,2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Total patches: 10 -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
