On Fri, Nov 4, 2022 at 2:32 PM Maxime Ripard <maxime@xxxxxxxxxx> wrote: > The UX500 PRCMU "clkout" clock implements a mux with a set_parent hook, > but doesn't provide a determine_rate implementation. > > This is a bit odd, since set_parent() is there to, as its name implies, > change the parent of a clock. However, the most likely candidate to > trigger that parent change is a call to clk_set_rate(), with > determine_rate() figuring out which parent is the best suited for a > given rate. > > The other trigger would be a call to clk_set_parent(), but it's far less > used, and it doesn't look like there's any obvious user for that clock. > > So, the set_parent hook is effectively unused, possibly because of an > oversight. However, it could also be an explicit decision by the > original author to avoid any reparenting but through an explicit call to > clk_set_parent(). It is actually set up from the device tree, typically like this: /* clkout1 from ACLK divided by 8 */ clocks = <&clkout_clk DB8500_CLKOUT_1 DB8500_CLKOUT_SRC_ACLK 8>; So the parent (source) and divisor comes in there. clk->source and clk->divider is already set up when clk_hw_register() is called. So set/get_parent() is never used on clkout. I think I just added the callbacks for completeness, should we delete them altogether? The patch is probably fine as-is as well so Acked-by: Linus Walleij <linus.walleij@xxxxxxxxxx> Yours, Linus Walleij
