Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v3 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG
> binding
>
> On Fri, Nov 04, 2022 at 03:19:34PM +0000, Biju Das wrote:
> > Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > v2->v3:
> > * Removed Rb tag from Rob as there are some changes introduced.
> > * Added companion property, so that poeg can link with gpt device
> > * Documented renesas,id, as identifier for POEGG{A,B,C,D}.
> > * Updated the example.
> > v1->v2:
> > * Updated the description.
> > REF->v1:
> > * Modelled as pincontrol as most of its configuration is intended to be
> > static.
> > * Updated reg size in example.
> > ---
> > .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 86
> > +++++++++++++++++++
> > 1 file changed, 86 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> > b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> > new file mode 100644
> > index 000000000000..8adf01682de5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yam
> > +++ l
> > @@ -0,0 +1,86 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +
> > +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > +
> > +description: |
> > + The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT)
> > +can be
> > + disabled by using the port output enabling function for the GPT (POEG).
> > + Specifically, either of the following ways can be used.
> > + * Input level detection of the GTETRGA to GTETRGD pins.
> > + * Output-disable request from the GPT.
> > + * SSF bit setting(ie, by setting POEGGn.SSF to 1)
> > +
> > + The state of the GTIOCxA and the GTIOCxB pins when the output is
> > + disabled, are controlled by the GPT module.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-poeg # RZ/G2{L,LC}
> > + - renesas,r9a07g054-poeg # RZ/V2L
> > + - const: renesas,rzg2l-poeg
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + companion:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: phandle of a companion.
> > +
> > + renesas,id:
>
> Perhaps 'poeg' in the name.
OK, will use 'renesas,poeg-id'
>
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [ 0, 1, 2, 3 ]
> > + description: |
> > + POEG group index. Valid values are:
> > + <0> : POEG group A (default)
>
> default: 0
>
> Though a default for a required property doesn't make much sense...
OK will remove the default.
Cheers,
Biju
>
> > + <1> : POEG group B
> > + <2> : POEG group C
> > + <3> : POEG group D
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - power-domains
> > + - resets
> > + - renesas,id
> > + - companion
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + poeggd: poeg@10049400 {
> > + compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
> > + reg = <0x10049400 0x400>;
> > + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G044_POEG_D_RST>;
> > + renesas,id = <3>;
> > + companion = <&gpt>;
> > + };
> > --
> > 2.25.1
> >
> >
