Hi All,
Gentle ping. Are we happy with the patch series?
Please let me know.
Cheers,
Biju
> -----Original Message-----
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Sent: 28 October 2022 11:42
> To: Thierry Reding <thierry.reding@xxxxxxxxx>; Rob Herring
> <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@xxxxxxxxxx>; Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
> Cc: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>; Uwe Kleine-König <u.kleine-
> koenig@xxxxxxxxxxxxxx>; linux-pwm@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; Geert Uytterhoeven <geert+renesas@xxxxxxxxx>;
> Chris Paterson <Chris.Paterson2@xxxxxxxxxxx>; Biju Das
> <biju.das@xxxxxxxxxxxxxx>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@xxxxxxxxxxxxxx>; linux-renesas-soc@xxxxxxxxxxxxxxx
> Subject: [PATCH v9 0/2] Add support for RZ/G2L GPT
>
> RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
> (GPT32E). It supports the following functions
> * 32 bits × 8 channels
> * Up-counting or down-counting (saw waves) or up/down-counting
> (triangle waves) for each counter.
> * Clock sources independently selectable for each channel
> * Two I/O pins per channel
> * Two output compare/input capture registers per channel
> * For the two output compare/input capture registers of each channel,
> four registers are provided as buffer registers and are capable of
> operating as comparison registers when buffering is not in use.
> * In output compare operation, buffer switching can be at crests or
> troughs, enabling the generation of laterally asymmetric PWM waveforms.
> * Registers for setting up frame cycles in each channel (with capability
> for generating interrupts at overflow or underflow)
> * Generation of dead times in PWM operation
> * Synchronous starting, stopping and clearing counters for arbitrary
> channels
> * Starting, stopping, clearing and up/down counters in response to input
> level comparison
> * Starting, clearing, stopping and up/down counters in response to a
> maximum of four external triggers
> * Output pin disable function by dead time error and detected
> short-circuits between output pins
> * A/D converter start triggers can be generated (GPT32E0 to GPT32E3)
> * Enables the noise filter for input capture and external trigger
> operation
>
> This patch series aims to add basic pwm support for RZ/G2L GPT driver by
> creating separate logical channels for each IOs.
>
> v8->v9:
> * Added Rb tag from Rob.
> * deassert after devm_clk_get() to avoid reset stays deasserted,in case
> clk_get() fails.
> * Removed ch_offs from struct rzg2l_gpt_chip and use macro instead.
> * Removed clk_disable_unprepare() from probe as it is giving
> gpt_pclk already disabled warning in the error path.
> [ 0.915664] clk_core_disable+0x25c/0x274
> [ 0.915754] clk_disable+0x2c/0x44
> [ 0.915833] rzg2l_gpt_pm_runtime_suspend+0x1c/0x34
> [ 0.915938] pm_generic_runtime_suspend+0x28/0x40
> [ 0.916042] genpd_runtime_suspend+0xa8/0x2b0
> [ 0.916136] __rpm_callback+0x44/0x13c
> [ 0.916218] rpm_callback+0x64/0x70
> [ 0.916296] rpm_suspend+0x104/0x630
> [ 0.916374] pm_runtime_work+0xb4/0xbc
> [ 0.916456] process_one_work+0x288/0x6a
> v7->v8:
> * Removed Rb tags from Rob and Geert as it modelled as single GPT
> device handling multiple channels.
> * Updated description
> * Updated interrupts and interrupt-names properties
> * Updated binding example
> * Modelled as single PWM device handling multiple channels
> * Replaced shared reset->devm_reset_control_get_exclusive()
> * Added PM runtime callbacks
> * Updated PM handling and removed "pwm_enabled_by_bootloader" variable
> * Replaced iowrite32->writel and ioread32->readl
> * Updated prescale calculation
> * Introduced rzg2l_gpt_is_ch_enabled for checking enable status on both
> IO's
> * Moved enable/disable output pins from config->enable/disable.
> * Added rzg2l_gpt_cntr_need_stop() for caching prescalar/mode values.
> v6->v7:
> * Added the comment for cacheing rzg2l_gpt->state_period.
> * Fixed boundary values for pv and dc.
> * Added comment for modifying mode, prescaler, timer counter and buffer
> enable
> registers.
> * Fixed buffer overflow in get_state()
> * Removed unnecessary assignment of state->period value in get_state().
> * Fixed state->duty_cycle value in get_state().
> * Added a limitation for disabling the channels, when both channels used
> v5->v6:
> * Updated macros RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH and
> RZG2L_GTIOR_GTIOB_OUT_LO_END_TOGGLE_CMP_MATCH with computation
> involving FIELD_PREP macro.
> * Removed struct rzg2l_gpt_phase and started using RZG2L_GTCCR macro
> for duty_offset.
> * replaced misnomer real_period->state_period.
> * Added handling for values >= (1024 << 32) for both period
> and duty cycle.
> * Added comments for pwm {en,dis}abled by bootloader during probe.
> v4->v5:
> * Added Hardware manual details
> * Replaced the comment GTCNT->Counter
> * Removed the macros RZG2L_GPT_IO_PER_CHANNEL and chip.npwm directly
> used in probe.
> * Removed the unsed macro RZG2L_GTPR_MAX_VALUE
> * Added driver prefix for the type name and the variable.
> * Initialization of per_channel data moved from request->probe.
> * Updated clr parameter for rzg2l_gpt_modify for Start count.
> * Started using mutex and usage_count for handling shared
> period and prescalar for the 2 channels.
> * Updated the comment cycle->period.
> * Removed clk_disable from rzg2l_gpt_reset_assert_pm_disable()
> * Replaced pc->rzg2l_gpt.
> * Updated prescale calculation.
> * Moved pm_runtime_{get_sync,put} from {request,free}->{enable,disable}
> * Removed platform_set_drvdata as it is unused
> * Removed the variable pwm_enabled_by_bootloader
> * Added dev_err_probe in various probe error path.
> * Added an error message, if devm_pwmchip_add fails.
> v3->v4:
> * Changed the local variable type i from u16->u8 and prescaled_period_
> cycles from u64->u32 in calculate_prescale().
> * Replaced mul_u64_u64_div_u64()->mul_u64_u32_div()
> * Dropped the comma after the sentinel.
> * Add a variable to track pwm enabled by bootloader and added comments
> in probe().
> * Removed unnecessary rzg2l_gpt_reset_assert_pm_disable() from probe.
> * Replaced devm_clk_get()->devm_clk_get_prepared()
> * Removed devm_clk_get_optional_enabled()
> v2->v3:
> * Added Rb tag from Rob for the bindings.
> * Updated limitation section
> * Added prefix "RZG2L_" for all macros
> * Modified prescale calculation
> * Removed pwm_set_chip_data
> * Updated comment related to modifying Mode and Prescaler
> * Updated setting of prescale value in rzg2l_gpt_config()
> * Removed else branch from rzg2l_gpt_get_state()
> * removed the err label from rzg2l_gpt_apply()
> * Added devm_clk_get_optional_enabled() to retain clk on status,
> in case bootloader turns on the clk of pwm.
> * Replaced devm_reset_control_get_exclusive->devm_reset_control_get_shared
> as single reset shared between 8 channels.
> V1->v2:
> * Added '|' after 'description:' to preserve formatting.
> * Removed description for pwm_cells as it is common property.
> * Changed the reg size in example from 0xa4->0x100
> * Added Rb tag from Geert for bindings.
> * Added Limitations section
> * dropped "_MASK" from the define names.
> * used named initializer for struct phase
> * Added gpt_pwm_device into a flexible array member in rzg2l_gpt_chip
> * Revised the logic for prescale
> * Added .get_state callback
> * Improved error handling in rzg2l_gpt_apply
> * Removed .remove callback
> * Tested the driver with PWM_DEBUG enabled.
>
> RFC->v1:
> * Added Description in binding patch
> * Removed comments from reg and clock
> * replaced rzg2l_gpt_write_mask()->rzg2l_gpt_modify()
> * Added rzg2l_gpt_read() and updated macros
> * Removed dtsi patches, will send it separately
>
> RFC:
> *
>
> Biju Das (2):
> dt-bindings: pwm: Add RZ/G2L GPT binding
> pwm: Add support for RZ/G2L GPT
>
> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 378 +++++++++++++
> drivers/pwm/Kconfig | 11 +
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-rzg2l-gpt.c | 530 ++++++++++++++++++
> 4 files changed, 920 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg2l-
> gpt.yaml
> create mode 100644 drivers/pwm/pwm-rzg2l-gpt.c
>
> --
> 2.25.1
