[GIT PULL] clk: renesas: Updates for v6.2

[Geert Uytterhoeven <geert+renesas@xxxxxxxxx>]

	Hi Mike, Stephen,

The following changes since commit a9003f74f5a2f487e101f3aa1dd5c3d3a78c6999:

  clk: renesas: r8a779g0: Fix HSCIF parent clocks (2022-10-26 12:05:36 +0200)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.2-tag1

for you to fetch changes up to 02693e11611e082e3c4d8653e8af028e43d31164:

  clk: renesas: r9a06g032: Repair grave increment error (2022-11-01 10:15:28 +0100)

----------------------------------------------------------------
clk: renesas: Updates for v6.2

  - Round SD clock rate to improve parent clock selection,
  - Add Ethernet Switch and internal SASYNCPER clocks on R-Car S4-8,
  - Add DMA (SYS-DMAC), SPI (MSIOF), external interrupt (INTC-EX),
    serial (SCIF), PWM (PWM and TPU), SDHI, and HyperFLASH/QSPI (RPC-IF)
    clocks on R-Car V4H,
  - Add Multi-Function Timer Pulse Unit (MTU3a) clock and reset on
    RZ/G2L,
  - Fix endless loop on RZ/N1,
  - Miscellaneous fixes and improvements.

Note that this includes my previous pull request for
renesas-clk-fixes-for-v6.1-tag1, which you have already pulled.

Thanks for pulling!

----------------------------------------------------------------
Biju Das (2):
      clk: renesas: rzg2l: Support sd clk mux round operation
      clk: renesas: r9a07g044: Add MTU3a clock and reset entry

Geert Uytterhoeven (11):
      clk: renesas: r8a779g0: Add SYS-DMAC clocks
      clk: renesas: r8a779g0: Add MSIOF clocks
      clk: renesas: r8a779g0: Add INTC-EX clock
      Merge tag 'renesas-clk-fixes-for-v6.1-tag1'
      clk: renesas: r8a779g0: Add SCIF clocks
      clk: renesas: r8a779g0: Add PWM clock
      clk: renesas: r8a779g0: Add TPU clock
      clk: renesas: r8a779f0: Fix SD0H clock name
      clk: renesas: r8a779f0: Add SASYNCPER internal clock
      clk: renesas: r8a779g0: Add SDHI clocks
      clk: renesas: r8a779g0: Add RPC-IF clock

Lad Prabhakar (5):
      clk: renesas: rzg2l: Fix typo in function name
      clk: renesas: r9a07g044: Drop WDT2 clock and reset entry
      clk: renesas: r9a07g043: Drop WDT2 clock and reset entry
      clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc
      clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM

Marek Vasut (1):
      clk: renesas: r9a06g032: Repair grave increment error

Wolfram Sang (1):
      clk: renesas: r8a779a0: Fix SD0H clock name

Yoshihiro Shimoda (1):
      clk: renesas: r8a779f0: Add Ethernet Switch clocks

 drivers/clk/renesas/r8a779a0-cpg-mssr.c |  2 +-
 drivers/clk/renesas/r8a779f0-cpg-mssr.c | 12 +++++---
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 22 +++++++++++++--
 drivers/clk/renesas/r9a06g032-clocks.c  |  3 +-
 drivers/clk/renesas/r9a07g043-cpg.c     |  5 ----
 drivers/clk/renesas/r9a07g044-cpg.c     | 10 +++----
 drivers/clk/renesas/rzg2l-cpg.c         | 49 +++++++++++++++++++--------------
 drivers/clk/renesas/rzg2l-cpg.h         |  4 +++
 8 files changed, 67 insertions(+), 40 deletions(-)

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds