Hi Prabhakar, On Thu, Oct 20, 2022 at 12:02 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > On the AX45MP core, cache coherency is a specification option so it may > not be supported. In this case DMA will fail. As a workaround, firstly we > allocate a global dma coherent pool from which DMA allocations are taken > and marked as non-cacheable + bufferable using the PMA region as specified > in the device tree. Synchronization callbacks are implemented to > synchronize when doing DMA transactions. > > The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) > block that allows dynamic adjustment of memory attributes in the runtime. > It contains a configurable amount of PMA entries implemented as CSR > registers to control the attributes of memory locations in interest. > > Below are the memory attributes supported: > * Device, Non-bufferable > * Device, bufferable > * Memory, Non-cacheable, Non-bufferable > * Memory, Non-cacheable, Bufferable > * Memory, Write-back, No-allocate > * Memory, Write-back, Read-allocate > * Memory, Write-back, Write-allocate > * Memory, Write-back, Read and Write-allocate > > This patch adds support to configure the memory attributes of the memory > regions as passed from the l2 cache node and exposes the cache management > ops. > > More info about PMA (section 10.3): > http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > This feature is based on the work posted [0] by Vincent Chen > <vincentc@xxxxxxxxxxxxx> for the Andes AndeStart RISC-V CPU. > > [0] https://lore.kernel.org/lkml/1540982130-28248-1-git-send-email-vincentc@xxxxxxxxxxxxx/ > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Thanks for your patch! > --- a/arch/riscv/mm/dma-noncoherent.c > +++ b/arch/riscv/mm/dma-noncoherent.c > @@ -24,13 +24,25 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, > > switch (dir) { > case DMA_TO_DEVICE: > +#ifdef CONFIG_ERRATA_THEAD_CMO > ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); > +#elif CONFIG_AX45MP_L2_CACHE "#elif defined(CONFIG_AX45MP_L2_CACHE)" (everywhere) Else it may fail with: error: "CONFIG_AX45MP_L2_CACHE" is not defined, evaluates to 0 [-Werror=undef] > + ALT_CMO_OP(ax45mp_cpu_dma_wb_range, vaddr, size, 0x0); > +#endif Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
