On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs. > We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > v4 -> v5 > * Sorted as per SoC name > * Included RB tag from Conor > > v3 -> v4 > * Dropped SOC_RENESAS_RZFIVE config option > * Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs > under ARCH_RENESAS > * Updated commit message > * Dropped RB tag > * Used riscv instead of RISC-V in subject line > > v2 -> v3 > * Included RB tag from Geert > > v1 -> v2 > * No Change > --- > arch/riscv/Kconfig.socs | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 69774bb362d6..75fb0390d6bd 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE > help > This enables support for Microchip PolarFire SoC platforms. > > +config ARCH_RENESAS > + bool "Renesas RISC-V SoCs" > + help > + This enables support for the RISC-V based Renesas SoCs. > + Looks good. Reviewed-by: Guo Ren <guoren@xxxxxxxxxx> > config SOC_SIFIVE > bool "SiFive SoCs" > select SERIAL_SIFIVE if TTY > -- > 2.25.1 > -- Best Regards Guo Ren
