Hi Geert, Thank you for the review. On Fri, Oct 28, 2022 at 12:35 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Wed, Oct 26, 2022 at 12:06 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that r9a07g043.dtsi > > can be shared with RZ/Five (RISC-V SoC). > > > > Below are the changes due to which SoC specific parts are moved to > > r9a07g043u.dtsi: > > - RZ/G2UL has Cortex-A55 (ARM64) whereas the RZ/Five has AX45MP (RISC-V) > > - RZ/G2UL has GICv3 as interrupt controller whereas the RZ/Five has PLIC > > - RZ/G2UL has interrupts for SYSC block whereas interrupts are missing > > for SYSC block on RZ/Five > > - RZ/G2UL has armv8-timer whereas the RZ/Five has riscv-timer > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > i.e. will queue in renesas-devel for v6.2. > > > --- > > RFC->v2 > > * Updated commit message about timer > > Right. And I'll add while applying: > > - RZ/G2UL has PSCI whereas RZ/Five have OpenSBI > That makes sense, thanks. Cheers, Prabhakar
