Quoting Geert Uytterhoeven (2022-10-07 06:09:59) > Hi Mike, Stephen, > > This patch series adds the various SASYNCPER clocks (used by modules > that must not be affected by Spread Spectrum and/or Fractional > Multiplication), and most of its derived module clocks (serial and PWM) > on the R-Car V4H (R8A7799G0) SoC. > > As the second patch is a fix, and the first patch is a dependency (also > for a related DT fix), I plan to queue the first two patches in > renesas-clk-fixes for v6.1. > I plan to queue the last three patches in renesas-clk for v6.2. > > Thanks for your comments! > > Geert Uytterhoeven (5): > clk: renesas: r8a779g0: Add SASYNCPER clocks > clk: renesas: r8a779g0: Fix HSCIF parent clocks > clk: renesas: r8a779g0: Add SCIF clocks > clk: renesas: r8a779g0: Add PWM clock > clk: renesas: r8a779g0: Add TPU clock > Thanks for the heads up Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>
