Hi Guo, On Wed, Oct 5, 2022 at 2:29 AM Guo Ren <guoren@xxxxxxxxxx> wrote: > > On Tue, Oct 4, 2022 at 6:32 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > On the AX45MP core, cache coherency is a specification option so it may > > not be supported. In this case DMA will fail. As a workaround, firstly we > > allocate a global dma coherent pool from which DMA allocations are taken > > and marked as non-cacheable + bufferable using the PMA region as specified > > in the device tree. Synchronization callbacks are implemented to > > synchronize when doing DMA transactions. > > > > The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) > > block that allows dynamic adjustment of memory attributes in the runtime. > > It contains a configurable amount of PMA entries implemented as CSR > > registers to control the attributes of memory locations in interest. > > > > Below are the memory attributes supported: > > * Device, Non-bufferable > > * Device, bufferable > > * Memory, Non-cacheable, Non-bufferable > > * Memory, Non-cacheable, Bufferable > > * Memory, Write-back, No-allocate > > * Memory, Write-back, Read-allocate > > * Memory, Write-back, Write-allocate > > * Memory, Write-back, Read and Write-allocate > Seems Svpbmt's PMA, IO, and NC wouldn't fit your requirements, could > give a map list of the types of Svpbmt? And give out what you needed, > but Svpbmt can't. > Sorry I didn't get what you meant here, could you please elaborate. > Here is the Linux dma type to Svpbmt map: > PMA -> Normal > IO -> ioremap, pgprot_noncached > NC -> pgprot_writecombine > > How about AX45MP? > Svpbmt extension is not supported on AX45MP (reported by riscv_isa_extension_available()) Cheers, Prabhakar
