Hi Prabhakar, On Tue, Oct 4, 2022 at 12:32 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > describes the L2 cache block. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml Not andestech,ax45mp-cache.yaml? > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2022 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/renesas/r9a07g043f-l2-cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive L2 Cache Controller Andestech AX45MP? > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > + > +description: > + A level-2 cache (L2C) is used to improve the system performance by providing > + a larger amount of cache line entries and reasonable access delays. The L2C > + is shared between cores, and a non-inclusive non-exclusive policy is used. > + > +properties: > + compatible: > + items: > + - const: andestech,ax45mp-cache > + - const: cache This makes the schema apply to any node which is compatible with "cache", cfr. the report from Rob's bot. You need a select block to avoid that, cfr. Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
