Hi Uwe,
> Subject: [PATCH v7 2/2] pwm: Add support for RZ/G2L GPT
>
> RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit
> timer (GPT32E). It supports the following functions
> * 32 bits × 8 channels
> * Up-counting or down-counting (saw waves) or up/down-counting
> (triangle waves) for each counter.
> * Clock sources independently selectable for each channel
> * Two I/O pins per channel
> * Two output compare/input capture registers per channel
> * For the two output compare/input capture registers of each channel,
> four registers are provided as buffer registers and are capable of
> operating as comparison registers when buffering is not in use.
> * In output compare operation, buffer switching can be at crests or
> troughs, enabling the generation of laterally asymmetric PWM
> waveforms.
> * Registers for setting up frame cycles in each channel (with
> capability
> for generating interrupts at overflow or underflow)
> * Generation of dead times in PWM operation
> * Synchronous starting, stopping and clearing counters for arbitrary
> channels
> * Starting, stopping, clearing and up/down counters in response to
> input
> level comparison
> * Starting, clearing, stopping and up/down counters in response to a
> maximum of four external triggers
> * Output pin disable function by dead time error and detected
> short-circuits between output pins
> * A/D converter start triggers can be generated (GPT32E0 to GPT32E3)
> * Enables the noise filter for input capture and external trigger
> operation
>
> This patch adds basic pwm support for RZ/G2L GPT driver by creating
> separate logical channels for each IOs.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v6->v7:
> * Added the comment for cacheing rzg2l_gpt->state_period.
> * Fixed boundary values for pv and dc.
> * Added comment for modifying mode, prescaler, timer counter and
> buffer enable
> registers.
> * Fixed buffer overflow in get_state()
> * Removed unnecessary assignment of state->period value in
> get_state().
> * Fixed state->duty_cycle value in get_state().
> * Added a limitation for disabling the channels, when both channels
> used.
> v5->v6:
> * Updated macros RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH and
> RZG2L_GTIOR_GTIOB_OUT_LO_END_TOGGLE_CMP_MATCH with computation
> involving FIELD_PREP macro.
> * Removed struct rzg2l_gpt_phase and started using RZG2L_GTCCR macro
> for duty_offset.
> * replaced misnomer real_period->state_period.
> * Added handling for values >= (1024 << 32) for both period
> and duty cycle.
> * Added comments for pwm {en,dis}abled by bootloader during probe.
> v4->v5:
> * Added Hardware manual details
> * Replaced the comment GTCNT->Counter
> * Removed the macros RZG2L_GPT_IO_PER_CHANNEL and chip.npwm directly
> used in probe.
> * Removed the unsed macro RZG2L_GTPR_MAX_VALUE
> * Added driver prefix for the type name and the variable.
> * Initialization of per_channel data moved from request->probe.
> * Updated clr parameter for rzg2l_gpt_modify for Start count.
> * Started using mutex and usage_count for handling shared
> period and prescalar for the 2 channels.
> * Updated the comment cycle->period.
> * Removed clk_disable from rzg2l_gpt_reset_assert_pm_disable()
> * Replaced pc->rzg2l_gpt.
> * Updated prescale calculation.
> * Moved pm_runtime_{get_sync,put} from {request,free}-
> >{enable,disable}
> * Removed platform_set_drvdata as it is unused
> * Removed the variable pwm_enabled_by_bootloader
> * Added dev_err_probe in various error paths in probe.
> * Added an error message, if devm_pwmchip_add() fails.
> v3->v4:
> * Changed the local variable type i from u16->u8 and
> prescaled_period_
> cycles from u64->u32 in calculate_prescale().
> * Replaced mul_u64_u64_div_u64()->mul_u64_u32_div()
> * Dropped the comma after the sentinel.
> * Add a variable to track pwm enabled by bootloader and added
> comments
> in probe().
> * Removed unnecessary rzg2l_gpt_reset_assert_pm_disable() from probe.
> * Replaced devm_clk_get()->devm_clk_get_prepared()
> * Removed devm_clk_get_optional_enabled()
> v2->v3:
> * Updated limitation section
> * Added prefix "RZG2L_" for all macros
> * Modified prescale calculation
> * Removed pwm_set_chip_data
> * Updated comment related to modifying Mode and Prescaler
> * Updated setting of prescale value in rzg2l_gpt_config()
> * Removed else branch from rzg2l_gpt_get_state()
> * removed the err label from rzg2l_gpt_apply()
> * Added devm_clk_get_optional_enabled() to retain clk on status,
> in case bootloader turns on the clk of pwm.
> * Replaced devm_reset_control_get_exclusive-
> >devm_reset_control_get_shared
> as single reset shared between 8 channels.
> v1->v2:
> * Added Limitations section
> * dropped "_MASK" from the define names.
> * used named initializer for struct phase
> * Added gpt_pwm_device into a flexible array member in rzg2l_gpt_chip
> * Revised the logic for prescale
> * Added .get_state callback
> * Improved error handling in rzg2l_gpt_apply
> * Removed .remove callback
> * Tested driver with PWM_DEBUG enabled
> RFC->V1:
> * Updated macros
> * replaced rzg2l_gpt_write_mask()->rzg2l_gpt_modify()
> * Added rzg2l_gpt_read()
> ---
> drivers/pwm/Kconfig | 11 +
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-rzg2l-gpt.c | 423
> ++++++++++++++++++++++++++++++++++++
> 3 files changed, 435 insertions(+)
> create mode 100644 drivers/pwm/pwm-rzg2l-gpt.c
>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index
> 60d13a949bc5..2723a3e9ff65 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -481,6 +481,17 @@ config PWM_ROCKCHIP
> Generic PWM framework driver for the PWM controller found on
> Rockchip SoCs.
>
> +config PWM_RZG2L_GPT
> + tristate "Renesas RZ/G2L General PWM Timer support"
> + depends on ARCH_RENESAS || COMPILE_TEST
> + depends on HAS_IOMEM
> + help
> + This driver exposes the General PWM Timer controller found in
> Renesas
> + RZ/G2L like chips through the PWM API.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-rzg2l-gpt.
> +
> config PWM_SAMSUNG
> tristate "Samsung PWM support"
> depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS ||
> COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index 7bf1a29f02b8..cac39b18d1ee 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_PWM_RASPBERRYPI_POE) += pwm-
> raspberrypi-poe.o
> obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
> obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
> obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
> +obj-$(CONFIG_PWM_RZG2L_GPT) += pwm-rzg2l-gpt.o
> obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
> obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
> obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
> new file mode 100644 index 000000000000..c4e011f2a843
> --- /dev/null
> +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> @@ -0,0 +1,423 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Renesas RZ/G2L General PWM Timer (GPT) driver
> + *
> + * Copyright (C) 2022 Renesas Electronics Corporation
> + *
> + * Hardware manual for this IP can be found here
> + *
> +https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-
> use
> +rs-manual-hardware-0?language=en
> + *
> + * Limitations:
> + * - Counter must be stopped before modifying Mode and Prescaler.
> + * - When PWM is disabled, the output is driven to inactive.
> + * - While the hardware supports both polarities, the driver (for
> now)
> + * only handles normal polarity.
> + * - When both channels are used, disabling the channel on one stops
> the
> + * other.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/limits.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/pwm.h>
> +#include <linux/reset.h>
> +#include <linux/time.h>
> +
> +#define RZG2L_GTCR 0x2c
> +#define RZG2L_GTUDDTYC 0x30
> +#define RZG2L_GTIOR 0x34
> +#define RZG2L_GTBER 0x40
> +#define RZG2L_GTCNT 0x48
> +#define RZG2L_GTCCRA 0x4c
> +#define RZG2L_GTCCRB 0x50
> +#define RZG2L_GTPR 0x64
> +
> +#define RZG2L_GTCR_CST BIT(0)
> +#define RZG2L_GTCR_MD GENMASK(18, 16)
> +#define RZG2L_GTCR_TPCS GENMASK(26, 24)
> +
> +#define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE FIELD_PREP(RZG2L_GTCR_MD, 0)
> +
> +#define RZG2L_GTUDDTYC_UP BIT(0)
> +#define RZG2L_GTUDDTYC_UDF BIT(1)
> +#define RZG2L_UP_COUNTING (RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF)
> +
> +#define RZG2L_GTIOR_GTIOA GENMASK(4, 0)
> +#define RZG2L_GTIOR_GTIOB GENMASK(20, 16)
> +#define RZG2L_GTIOR_OAE BIT(8)
> +#define RZG2L_GTIOR_OBE BIT(24)
> +
> +#define RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE 0x07
> +#define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE 0x1b
> +
> +#define RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH \
> + (RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE | RZG2L_GTIOR_OAE) #define
> +RZG2L_GTIOR_GTIOA_OUT_LO_END_TOGGLE_CMP_MATCH \
> + (RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE | RZG2L_GTIOR_OAE) #define
> +RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH \
> + (FIELD_PREP(RZG2L_GTIOR_GTIOB,
> RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE) |
> +RZG2L_GTIOR_OBE) #define
> RZG2L_GTIOR_GTIOB_OUT_LO_END_TOGGLE_CMP_MATCH \
> + (FIELD_PREP(RZG2L_GTIOR_GTIOB,
> RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) |
> +RZG2L_GTIOR_OBE)
> +
> +#define RZG2L_GTCCR(i) (0x4c + 4 * (i))
> +
> +struct rzg2l_gpt_chip {
> + struct pwm_chip chip;
> + void __iomem *mmio;
> + struct reset_control *rstc;
> + struct clk *clk;
> + struct mutex lock;
> + u32 user_count;
> + u32 state_period;
> + unsigned long rate;
> + bool pwm_enabled_by_bootloader;
> +};
> +
> +static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct
> pwm_chip
> +*chip) {
> + return container_of(chip, struct rzg2l_gpt_chip, chip); }
> +
> +static void rzg2l_gpt_write(struct rzg2l_gpt_chip *rzg2l_gpt, u32
> reg,
> +u32 data) {
> + iowrite32(data, rzg2l_gpt->mmio + reg); }
> +
> +static u32 rzg2l_gpt_read(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg)
> {
> + return ioread32(rzg2l_gpt->mmio + reg); }
> +
> +static void rzg2l_gpt_modify(struct rzg2l_gpt_chip *rzg2l_gpt, u32
> reg, u32 clr,
> + u32 set)
> +{
> + rzg2l_gpt_write(rzg2l_gpt, reg,
> + (rzg2l_gpt_read(rzg2l_gpt, reg) & ~clr) | set); }
> +
> +static u8 rzg2l_calculate_prescale(struct rzg2l_gpt_chip *rzg2l_gpt,
> + u64 period_cycles)
> +{
> + u32 prescaled_period_cycles;
> + u8 prescale;
> +
> + prescaled_period_cycles = period_cycles >> 32;
> +
> + if (prescaled_period_cycles >= 256)
> + prescale = 5;
> + else
> + prescale = (roundup_pow_of_two(prescaled_period_cycles + 1)
> + 1) / 2;
This algorithm won't give desired result.
prescaled_period_cycles Expected result
0 ->0
1..3 ->1
4..15 ->2
16..63 ->3
64..255 ->4
256 > ->5
I believe we need a for loop like in patch[4] to get the desired result.
Please correct me if you think otherwise.
[4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220728162526.330542-3-biju.das.jz@xxxxxxxxxxxxxx/
Cheers,
Biju
