Hi Andrew, > From: Andrew Lunn, Sent: Wednesday, September 28, 2022 9:01 PM > > > > How do you direct a frame from the > > > CPU out a specific user port? Via the DMA ring you place it into, or > > > do you need a tag on the frame to indicate its egress port? > > > > Via the DMA ring. > > Are there bits in the ring descriptor which indicate the user port? > Can you set these bits to some other value which causes the switch to > use its MAC table to determine the egress interface? I'm sorry, I misunderstood the hardware behaviors. 1) From CPU to user port: CPU sends a frame to all user ports. 2) From user port to CPU: each user port sends a frame to each DMA ring. About the 1) above, the switch can have MAC tables and sends a frame to a specific user port. However, the driver doesn't support it. > > > > The PHY is 88E2110 on my environment, so Linux has a driver in > > > > drivers/net/phy/marvell10g.c. However, I guess this is related to > > > > configuration of the PHY chip on the board, it needs to change > > > > the host 7interface mode, but the driver doesn't support it for now. > > > > > > Please give us more details. The marvell10g driver will change its > > > host side depending on the result of the line side negotiation. It > > > changes the value of phydev->interface to indicate what is it doing on > > > its host side, and you have some control over what modes it will use > > > on the host side. You can probably define its initial host side mode > > > via phy-mode in DT. > > > > I'm sorry, my explanation was completely wrong. > > My environment needs to change default MAC speed from 2.5G/5G to 1000M. > > The register of 88E2110 is 31.F000.7:6. And sets the register to "10" (1000 Mbps). > > (Default value of the register is "11" (Speed controlled by other register).) > > Is this the host side speed? The speed of the SERDES between the > switch and the PHY? Yes. > Normally, the PHY determines this from the line > side. If the line side is using 2.5G, it will set the host side to > 2500BaseX. If the line side is 1G, the host side is likely to be > SGMII. > > You have already removed speeds you don't support. So the PHY will not > negotiate 2.5G or 5G. It is limited to 1G. So it should always have > the host side as SGMII. This should be enough to make it work. I see. However, if I dropped specific registers setting, it doesn't work correctly. I'll investigate why removing speeds of PHY didn't work. Best regards, Yoshihiro Shimoda > Andrew
