Hi Krzysztof, On Thu, Sep 8, 2022 at 12:39 PM Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> wrote: > > On 06/09/2022 01:04, Lad Prabhakar wrote: > > Document the CSI-2 block which is part of CRU found in Renesas > > RZ/G2L (and alike) SoCs. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx> > > --- > > v1 -> v2 > > * Dropped media prefix from subject > > * Renamed node name csi20 -> csi > > * Used 4 spaces for indentation in example node > > * Dropped reset-names and interrupt-names properties > > * Dropped oneOf from compatible > > * Included RB tag from Laurent > > > > RFC v2 -> v1 > > * Fixed review comments pointed by Rob and Jacopo. > > > > RFC v1 -> RFC v2 > > * New patch > > --- > > .../bindings/media/renesas,rzg2l-csi2.yaml | 140 ++++++++++++++++++ > > 1 file changed, 140 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > new file mode 100644 > > index 000000000000..79beace4dec2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > @@ -0,0 +1,140 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (C) 2022 Renesas Electronics Corp. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver > > + > > +maintainers: > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > + > > +description: > > + The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L > > + (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction > > + with the Image Processing module, which provides the video capture capabilities. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - renesas,r9a07g044-csi2 # RZ/G2{L,LC} > > + - renesas,r9a07g054-csi2 # RZ/V2L > > + - const: renesas,rzg2l-csi2 > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Internal clock for connecting CRU and MIPI > > + - description: CRU Main clock > > + - description: CPU Register access clock > > + > > + clock-names: > > + items: > > + - const: sysclk > > + - const: vclk > > + - const: pclk > > One more: drop the "clk" suffixes. Remaining names could be made a bit > more readable. > The clock names are coming from the clock-list document provided along with the HW manual: - CRU_SYSCLK - CRU_VCLK - CRU_PCLK Ive dropped the CRU_ prefix, do you still want me to rename them? Cheers, Prabhakar
