On 21/09/2022 09:46, Geert Uytterhoeven wrote:
> Hi Rob, Krzysztof,
>
> This is a topic that came up at the RISC-V BoF at Plumbers, and it was
> suggested to bring it up with you.
I guess you also need SoC maintainers as well (+Cc Arnd and Olof). :)
>
> The same SoC may be available with either RISC-V or other (e.g. ARM) CPU
> cores (an example of this are the Renesas RZ/Five and RZ/G2UL SoCs).
> To avoid duplication, we would like to have:
> - <riscv-soc>.dtsi includes <base-soc>.dtsi,
> - <arm-soc>.dtsi includes <base-soc>.dtsi.
>
> Unfortunately RISC-V and ARM typically use different types of interrupt
> controllers, using different bindings (e.g. 2-cell vs. 3-cell), and
> possibly using different interrupt numbers. Hence the interrupt-parent
> and interrupts{-extended} properties should be different, too.
>
> Possible solutions[1]:
> 1. interrupt-map
>
> 2. Use a SOC_PERIPHERAL_IRQ() macro in interrupts properties in
> <base-soc>.dtsi, with
> - #define SOC_PERIPHERAL_IRQ(nr, na) nr // RISC-V
> - #define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI na // ARM
> Note that the cpp/dtc combo does not support arithmetic, so even
> the simple case where nr = 32 + na cannot be simplified.
What do you mean? Macros support string concatenation and simple
arithmetic like adding numbers. I just tested it.
>
> 3. Wrap inside RISCV() and ARM() macros, e.g.:
>
> RISCV(interrupts = <412 IRQ_TYPE_LEVEL_HIGH>;)
> ARM(interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;)
>
> Cfr. ARM() and THUMB() in arch/arm/include/asm/unified.h, as used
> to express the same operation using plain ARM or ARM Thumb
> instructions.
>
> Personally, I'm leaning towards the third solution, as it is the most
> flexible, and allows us to extend to more than 2 interrupt controllers.
>
> Note that this is actually not a new issue. For years, ARM SoCs have
> existed with multiple types of cores on the same die, using Cortex-A
> cores for the application, and Cortex-R/SuperH/V850/... cores for
> real-time and/or baseband operation. So far this wasn't an issue, as
> only the Cortex-A cores ran Linux, and we ignored the other cores (and
> the related interrupt controllers and hierarchy) in DT.
>
> What do you think?
> Thanks for your comments!
If it is doable with a macro (option 2), I would vote for this. Assuming
of course that the interrupts differ only by GIC_SPI/PPI and base
number. I guess this should be the case if this is the same SoC?
Best regards,
Krzysztof
