Hi Bjorn, Thank you for your review! > From: Bjorn Helgaas, Sent: Wednesday, September 21, 2022 5:08 AM > > On Mon, Sep 05, 2022 at 04:12:48PM +0900, Yoshihiro Shimoda wrote: > > Add macros defining Maximum Link Width bits in Link Capabilities > > Register. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> > > --- > > include/uapi/linux/pci_regs.h | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > index 57b8e2ffb1dd..c9f4c452e210 100644 > > --- a/include/uapi/linux/pci_regs.h > > +++ b/include/uapi/linux/pci_regs.h > > @@ -538,6 +538,13 @@ > > #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ > > #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ > > #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */ > > +#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */ > > +#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */ > > +#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */ > > +#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */ > > +#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */ > > +#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */ > > +#define PCI_EXP_LNKCAP_MLW_X32 0x00000200 /* Maximum Link Width x32 */ > > In PCIe r6.0, x32 is mentioned a few times, but not actually defined > for Link Capabilities. Has it been defined in an ECN or something? I should have looked PCIe r6.0, but I looked PCIe r4.0 v1.0 and it mentioned x32. So, I wrote the x32 macro. I'll drop PCI_EXP_LNKCAP_MLW_X32 on v6 patch. Best regards, Yoshihiro Shimoda
