Hi Prabhakar,
> Subject: Re: [PATCH] clk: renesas: r9a07g044: Add WDT2 clocks to
> critical list
>
> Hi Biju,
>
> On Mon, Sep 19, 2022 at 2:35 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> >
> > Hi Prabhakar,
> >
> > > Subject: [PATCH] clk: renesas: r9a07g044: Add WDT2 clocks to
> > > critical list
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Add the WDT2 clocks to r9a07g044_crit_mod_clks[] list as WDT CH2
> is
> > > specifically to check the operation of Cortex-M33 CPU on the
> > > RZ/{G2L, G2LC, V2L} SoCs and we dont want to turn off the clocks
> of
> > > WDT2 if it isn't enabled by Cortex-A55.
> > >
> > > This patch is in preparation to disable WDT CH2 from the RZ/G2L
> > > (alike
> > > SoCs) DTS/I by default.
> > >
> > > Reported-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > ---
> > > drivers/clk/renesas/r9a07g044-cpg.c | 2 ++
> > > 1 file changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/clk/renesas/r9a07g044-cpg.c
> > > b/drivers/clk/renesas/r9a07g044-cpg.c
> > > index 02a4fc41bb6e..cf9b1bd73792 100644
> > > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> > > @@ -412,6 +412,8 @@ static const unsigned int
> > > r9a07g044_crit_mod_clks[] __initconst = {
> > > MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
> > > MOD_CLK_BASE + R9A07G044_IA55_CLK,
> > > MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
> > > + MOD_CLK_BASE + R9A07G044_WDT2_PCLK,
> > > + MOD_CLK_BASE + R9A07G044_WDT2_CLK,
> >
> > Do we need to turn on this clock unnecessarily?
> >
> No, this is in preparation to disable WDT2 by default from RZ/G2L{C}
> DTS/I.
But that will make WDT2 device is not enabled, but unnecessarily the clk is on.
Not sure, If we have any use case for wdt2 controlling from CA-55??
If there is no use case, why can't we remove it from SoC dtsi and clock tables,
that why we don't unnecessarily use this clock anymore??
Cheers,
Biju
