On Thu, Sep 15, 2022 at 11:44 PM <Conor.Dooley@xxxxxxxxxxxxx> wrote: > > > > On 15/09/2022 23:41, Lad, Prabhakar wrote: > > Hi Conor, > > > > Thank you for the review. > > > > On Thu, Sep 15, 2022 at 10:56 PM <Conor.Dooley@xxxxxxxxxxxxx> wrote: > >> > >> On 15/09/2022 19:15, Prabhakar wrote: > >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >>> > >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > >>> > >>> Enable the minimal blocks required for booting the Renesas RZ/Five > >>> SMARC EVK with initramfs. > >>> > >>> Below are the blocks enabled: > >>> - CPG > >>> - CPU0 > >>> - DDR (memory regions) > >>> - PINCTRL > >>> - PLIC > >>> - SCIF0 > >>> > >>> Note we have deleted the nodes from the DT for which support needs to be > >>> added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier > >>> board DTS/I. > >> > >> idk, I am not sure what to think of this approach. > >> > >> What do you mean by "for which support needs to be added"? If the support > >> does not exist yet, then is surely you can just add the nodes and it will > >> be fine? > >> > > As pointed out previously, I am re-using the below files [1] (SoM) and > > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since > > [1] and [2] enable almost all the peripherals (status = okay) on the > > RZ/G2UL SMARC EVK which are supported. For example [1] enables SDHI0/1 > > this high speed block needs DMA and without cache management fixed on > > Andes core we cannot enable this on RZ/Five SoC so currently a > > placeholder is added for it in the RZ/FIve SoC DTSI and is deleted in > > the board DTS file. > > > > Below blocks suffer the cache management issue: > > - DMAC > > - ETH > > - SDHI > > - USB > > > > Rest of the blocks will be gradually enabled (as soon as this initial > > patchset is merged) along with the DT binding doc updates. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5 > > > Explanations are reasonable, but again - that information is important > and really needs to be included in the commit message etc. > Sure, I will update the commit message while sending the v4. Cheers, Prabhakar
